Hardware-efficient quantum error correction using concatenated bosonic qubits

To solve problems of practical importance, quantum computers will likely need to incorporate quantum error correction, where a logical qubit is redundantly encoded in many noisy physical qubits. The large physical-qubit overhead typically associated with error correction motivates the search for more hardware-efficient approaches. To this end, in this talk I will describe our recent superconducting circuit experiment realizing a logical qubit memory via the concatenation of encoded bosonic cat qubits with an outer repetition code. The cat qubits are passively protected against bit-flip errors, while phase-flip errors are corrected by the repetition code. The repetition code operates below threshold, with logical phase-flip error decreasing with code distance from 3 to 5. Concurrently, the logical bit-flip error is suppressed with increasing cat-qubit mean photon number. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 codes, and 1.65(3)% for the longer distance-5 code. Looking forward, I will also discuss the long-term prospects of this cat-qubit architecture, focusing on paths to reach algorithmically-relevant logical error rates. 

*We strongly encourage attendees to use their full name (and if possible, their UMD credentials) to join the zoom session.*